A conventional core cell in a NAND array memory device is described with reference to FIGS. 1A and 1B, which are simplified cross sectional diagrams of the conventional NAND array 10 having a floating gate memory cell 12. The memory cell 12 is a floating gate transistor having a control gate 14 separated from a polycrystalline silicon floating gate 16 by an upper insulating layer while floating gate 16 is separated from a substrate 18 by a lower insulating layer. The substrate includes n+ source regions 20, a p-doped body region 22, and an n+ drain region 24 as in a conventional NMOS enhancement mode transistor.
As illustrated in FIG. 1A, in order to program the conventional floating gate memory cell 10, control gate 14 is biased at a relatively high voltage of approximately 20 volts while body region 22 is rounded. The high voltage on the control gate 14 induces electrons from body region 22 to tunnel through the lower insulation layer and into floating gate 16 through a conventionally known process called Fowler-Nordheim tunneling. The floating gate 16 accumulates negative charge thereby increasing the threshold voltage of memory cell 12. As illustrated in FIG. 1B, erasing occurs by biasing the body region 22 at a high voltage of approximately 20 volts while the control gate 14 is grounded causing the electrons from floating gate 16 to tunnel through the lower insulation layer and into the body region 22. A NAND EEPROM based non-volatile flash memory architecture is described in U.S. Pat. No. 5,568,420, filed Nov. 30, 1994, which is herein incorporated by reference for all purposes.
Generally, a conventional NAND memory cell device, as described above, is a high density device subject to high voltage requirements. Although, the high density, high voltage characteristics are desirable traits in a NAND cell structure, these traits tend to make bit line to bit line isolation within the NAND structure more difficult. Specifically, since there is usually not enough margin for isolation between bit lines in the NAND array structure, the outdiffusion of impurities may result in low junction breakdown and bit line to bit line leakage.
Therefore, what is desired is an improved method for fabricating the NAND array structure which improves the reliability of the NAND memory cell structure by minimizing outdiffusion.